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Benny Åkesson (Publications)

Benny Åkesson (Publications)

Benny Åkesson (Publications)

PhD Eindhoven University of Technology, Netherlands
Collaborator PhD Researcher

Benny Akesson received his MSc degree at Lund Institute of Technology, Sweden in 2005 and a PhD from Eindhoven University of Technology, the Netherlands in 2010. Since then, he has been employed as a Researcher at Eindhoven University of Technology, Czech Technical University in Prague, and CISTER/INESC TEC Research Unit in Porto. He is a Professor by Special Appointment at the University of Amsterdam and holds the Chair of Design Methodologies for Cyber-physical systems since 2019.

Currently, Prof. Akesson is working as a Senior Research Fellow at ESI (TNO) in Eindhoven. His research interest is design methodologies for cyber-physical systems, in particular model-based engineering and real-time systems. He has published more than 60 peer-reviewed conference papers and journal articles, as well as two books about memory controllers for real-time embedded systems.

Benny was in CISTER from August 2012 - January 2013 and returned to the unit in July 2015.

 

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Books & Book Chapters
Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs CISTER-TR-160401 
Sven Goossens, Karthik Chandrasekar, Benny Åkesson, Kees Goossens2016, 202 pages.http://www.springer.com/gp/book/9783319320939
Journal Papers
Response time analysis of Multiframe mixed criticality systems with arbitrary deadlines CISTER-TR-200603 
Ishfaq Hussain, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarReal-Time Systems, Springer. Apr 2021, Volume 57, pp 141-189.
Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Server Execution Budgets CISTER-TR-200115 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Åkesson, Eduardo TovarACM Transactions on Embedded Computing Systems (TECS), Article No 109, ACM. Oct 2019, Volume 18, Issue 5s, pp 109:1-109:23.This article appears as part of the ESWEEK-TECS special issue and was presented at the International Conference on Embedded Software (EMSOFT) 2019.
Uneven memory regulation for scheduling IMA applications on multi-core platforms CISTER-TR-181131 
Muhammad Ali Awan, Pedro Souto, Benny Åkesson, Konstantinos Bletsas, Eduardo TovarReal-Time Systems, Springer. Apr 2019, Volume 55, Issue 2, pp 248-292.
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact) CISTER-TR-181107 
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDagstuhl Artifacts Series (DARTS), Article No 5, Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. 2018, Volume 4, Issue 2, pp 5:1-5:3.
Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requirements CISTER-TR-170702 
Anna Minaeva, Benny Åkesson, Zdeněk Hanzálek, Dakshina Dasari
ABSTRACT Additional Files: PDFOpen Access Version
IEEE Transactions on Computers, IEEE. 1, Jan, 2018, Volume 67, Issue 1, pp 115-129.
A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems CISTER-TR-160801 
Manil Dev Gomony, Jamie Garside, Benny Åkesson, Neil Audsley, Kees GoossensIEEE Transactions on Computers (TC), IEEE. Feb 2017, Volume 66, Issue 2, pp 212-225.
Reducing the Complexity of Dataflow Graphs using Slack-based Merging CISTER-TR-160607 
Hazem Ali, Sander Stuijk, Benny Åkesson, Luis Miguel PinhoACM Transactions on Design Automation of Electronic Systems (TODAES), Article No 24, ACM. Jan 2017, Volume 22, Issue 2, pp 24:1-24:22.
A framework for memory contention analysis in multi-core platforms CISTER-TR-150510 
Dakshina Dasari, Vincent Nélis, Benny ÅkessonReal-Time Systems (RTS), Springer. May 2016, Volume 52, Issue 3, pp 272-322. U.S.A..
Scalable and Efficient Configuration of Time-Division Multiplexed Resources CISTER-TR-151104 
Anna Minaeva, Benny Åkesson, Zdeněk Hanzálek, Přemysl ŠůchaaJournal of Systems and Software (jss), Elsevier. Mar 2016, Volume 113, pp 44-58.
Unified Overhead-aware Schedulability Analysis for Slot-based Task-splitting CISTER-TR-130201 
Paulo Baltarejo Sousa, Konstantinos Bletsas, Eduardo Tovar, Pedro Souto, Benny ÅkessonReal-Time Systems journal, Springer US. Jul 2014, Volume 50, Issue 4, pp 1-56.
Conference or Workshop Papers/Talks
Response time analysis of Multiframe mixed criticality systems CISTER-TR-190908 
Ishfaq Hussain, Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo Tovar27th International Conference on Real-Time Networks and Systems (RTNS 2019). 6 to 8, Nov, 2019, pp 8-18. Toulouse, France.Outstanding paper award
Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Server Execution Budgets CISTER-TR-190906 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Åkesson, Eduardo Tovar
ABSTRACTPDFPDF Additional Files: PDFPoster
ACM SIGBED International Conference on Embedded Software (EMSOFT 2019). 13 to 18, Oct, 2019, pp 109:1-109:23. New York, U.S.A..ACM Transactions on Embedded Computing Systems, Vol. 18, No. 5s, Article 109.
Memory Bandwidth Regulation for Multiframe Task Sets CISTER-TR-190629 
Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo Tovar25th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2019). 18 to 21, Aug, 2019. Hangzhou, China.
Uneven memory regulation for scheduling IMA applications on multi-core platforms CISTER-TR-190505 
Muhammad Ali Awan, Pedro Souto, Benny Åkesson, Konstantinos Bletsas, Eduardo Tovar
ABSTRACTPDFPDF Additional Files: PDFPoster
31st Conference on Real-Time Systems (ECRTS 2019). 9 to 12, Jul, 2019, J2C. Stuttgart, Germany.Journal to Conference paper (CISTER-TR-181131).
Decoupling Criticality and Importance in Mixed-Criticality Scheduling CISTER-TR-181119 
Konstantinos Bletsas, Muhammad Ali Awan, Pedro Souto, Benny Åkesson, Alan Burns, Eduardo Tovar6th International Workshop on Mixed Criticality Systems (WMC 2018). 11, Dec, 2018, pp 25-30. Nashville, U.S.A..WMC 2018 was held as part of RTSS 2018, Nashville, USA, 11-14 December.
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation CISTER-TR-180604 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018, Session 4: Support for Predictability, pp 111-117. Hakodate, Japan.
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers CISTER-TR-180401 
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo Tovar30th Euromicro Conference on Real-Time Systems (ECRTS 2018). 3 to 6, Jul, 2018, pp 2:1-2:22. Barcelona, Spain.Volume 106
Mixed-criticality Scheduling with Memory Bandwidth Regulation CISTER-TR-171201 
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDesign, Automation and Test in Europe 2018 (DATE 2018). 19 to 23, Mar, 2018, pp 1277-1282. Dresden, Germany.
Mixed-Criticality Systems with Partial Lockdown and Cache Reclamation Upon Mode Change CISTER-TR-170507 
Konstantinos Bletsas, Muhammad Ali Awan, Pedro Souto, Benny Åkesson, Eduardo Tovar
ABSTRACTPDFPDF Additional Files: PDFPoster, PDFPresentation
Work in Progress Session, 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). 27 to 30, Jun, 2017, pp 22-24. Dubrovnik, Croatia.http://www.ecrts.org/fileadmin/files_ecrts17/Proceedings_ECRTS-WiP2017.pdf
Mixed-criticality Scheduling with Dynamic Redistribution of Shared Cache CISTER-TR-170202 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar29th Euromicro Conference on Real-Time Systems (ECRTS 2017). 27 to 30, Jun, 2017, Main track, pp 18:1-18:21. Dubrovnik, Croatia.
Combining Dataflow Applications and Real-time Task Sets on Multi-core Platforms CISTER-TR-170405 
Hazem Ali, Benny Åkesson, Luis Miguel Pinho20th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2017). 12 to 13, Jun, 2017, pp 60-63. Sankt Goar, Germany.
Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform CISTER-TR-170302 
Matthias Becker, Borislav Nikolic, Dakshina Dasari, Benny Åkesson, Vincent Nélis, Moris Behnam, Thomas Nolte24th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2017). 18 to 20, Apr, 2017, pp 101-112. Pittsburgh, U.S.A..
Mixed-criticality scheduling with memory regulation CISTER-TR-160604 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar, Jibran Ali
ABSTRACTPDFPDF Additional Files: PDFPoster
Work in Progress Session, 28th Euromicro Conference on Real-Time Systems (ECRTS 2016). 5 to 8, Jul, 2016. Toulouse, France.
Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform CISTER-TR-160505 
Matthias Becker, Dakshina Dasari, Borislav Nikolic, Benny Åkesson, Vincent Nélis, Thomas Nolte28th Euromicro Conference on Real-Time Systems (ECRTS 2016). 5 to 8, Jul, 2016. Toulouse, France.
Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems CISTER-TR-160503 
Syed Aftab Rashid, Geoffrey Nelissen, Damien Hardy, Benny Åkesson, Isabelle Puaut, Eduardo Tovar28th Euromicro Conference on Real-Time Systems (ECRTS 2016). 5 to 8, Jul, 2016. Toulouse, France.Outstanding Paper Award
Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers CISTER-TR-160202 
Yonghui Li, Benny Åkesson, Kees GoossensReal-Time and Embedded Technology and Applications Symposium (RTAS 2016). 11 to 14, Apr, 2016, Track 3: Embedded Systems Design for Real-Time Applications. Vienna, Austria.
Mode-Controlled Data-Flow Modeling of Real-Time Memory Controllers CISTER-TR-150901 
Yonghui Li, Hrishikesh Salunkhe, João Bastos, Orlando Moreira, Benny Åkesson, Kees Goossens13th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia 2015). 8 to 9, Oct, 2015. Amsterdam, Netherlands.Best Paper Award
Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs CISTER-TR-141102 
Hazem Ali, Benny Åkesson, Luis Miguel Pinho23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2015). 4 to 6, Mar, 2015. Turku, Finland.
Critical-Path-First Based Allocation of Real-Time Streaming Applications on 2D Mesh-Type Multi-Cores CISTER-TR-130606 
Hazem Ali, Luis Miguel Pinho, Benny Åkesson19th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2013). 19 to 21, Aug, 2013. Taipei, Taiwan.
Identifying the Sources of Unpredictability in COTS-based Multicore Systems CISTER-TR-130604 
Dakshina Dasari, Benny Åkesson, Vincent Nélis, Muhammad Ali Awan, Stefan M. Petters8th IEEE International Symposium on Industrial Embedded Systems (SIES 2013), IEEE. 19 to 21, Jun, 2013, pp 39-48. Porto, Portugal.
Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach CISTER-TR-130402 
Karthik Chandrasekar, Christian Weis, Benny Åkesson, Norbert Wehn, Kees Goossens50th ACM/EDAC/IEEE Design Automation Conference (DAC 2013), ACM New York. 29, May to 7, Jun, 2013, 23. Austin, U.S.A..
Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis CISTER-TR-130105 
Hardik Shah, Alois Knoll, Benny ÅkessonDesign, Automation & Test in Europe Conference & Exhibition (DATE 2013), IEEE. 18 to 22, Mar, 2013, pp 308-313. Grenoble, France.
Conservative Open-page Policy for Mixed Time-Criticality Memory Controllers CISTER-TR-130104 
Sven Goossens, Benny Åkesson, Kees GoossensDesign, Automation & Test in Europe Conference & Exhibition (DATE 2013), IEEE. 18 to 22, Mar, 2013, pp 525-530. Grenoble, France.
Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller CISTER-TR-130107 
Manil Dev Gomony, Benny Åkesson, Kees GoossensDesign, Automation & Test in Europe Conference & Exhibition (DATE 2013), EDA Consortium San Jose. 18 to 22, Mar, 2013, pp 1307-1312. Grenoble, France.
System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs CISTER-TR-130106 
Karthik Chandrasekar, Christian Weis, Benny Åkesson, Norbert Wehn, Kees GoossensDesign, Automation & Test in Europe Conference & Exhibition (DATE 2013), IEEE. 18 to 22, Mar, 2013, pp 236-241. Grenoble, France.
A Declarative Compositional Timing Analysis for Multicores Using the Latency-Rate Abstraction CISTER-TR-130108 
Vitor Rodrigues, Benny Åkesson, Simão Patrício Melo de Sousa, Mário Florido15th International Symposium on Practical Aspects of Declarative Languages (PADL '13), Springer Berlin Heidelberg. 21 to 22, Jan, 2013, 7752, pp 43-59. Rome, Italy.
Technical Reports
Technical Report: Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Server Execution Budgets CISTER-TR-190202 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Åkesson, Eduardo Tovar2019.
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation (Long Version) CISTER-TR-180603 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar28, Aug, 2018.
Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requirements CISTER-TR-181123 
Anna Minaeva, Benny Åkesson, Zdeněk Hanzálek, Dakshina Dasari2, Oct, 2017.
Mixed-criticality Scheduling with Dynamic Redistribution of Shared Cache CISTER-TR-181124 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Åkesson, Eduardo Tovar28, Apr, 2017.