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Syed Aftab Rashid (Publications)

Syed Aftab Rashid (Publications)

Syed Aftab Rashid (Publications)

PhD University of Porto, Portugal
Integrated PhD Researcher

Syed Aftab Rashid joined the CISTER research unit in 2015 as a Ph.D. student. He is currently an integrated Ph.D. researcher and serves as CISTER lead at VORTEX-CoLab. He completed his Ph.D. from the University of Porto, Portugal, in 2021.

His dissertation was on the timing analysis of multicore platforms for hard real-time systems with a focus on contention due to sharing of cache memories and interconnects.

Before joining CISTER, he received his M.Sc. in Electrical Engineering from the National University of Computer and Emerging Sciences (NUCES)-FAST, Islamabad, Pakistan in 2014.

He has worked on several international projects related to embedded system design and implementation. He has also co-authored several publications in reputed conferences (e.g., RTSS, ECRTS, RTCSA, DATE) and journals (e.g., Applied Energy). Aftab has also been a part of different conference organization committees including ECRTS, RTNS, and CPSWeek.

His research interests include real-time embedded systems, timing and scheduling analysis, resource contention, and multicore architectures' predictability.

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Thesis
Towards Timing Analysis of Multi-core Platforms for Hard Real-Time Systems CISTER-TR-210403 
Syed Aftab RashidPhD Thesis. 9, Apr, 2021. Porto.Presidente do Juri Doutor José Alfredo Ribeiro da Silva Matos, Professor Catedrático da FEUP
Vogais Doutor Sebastian Altmeyer, Professor da University of Augsburg, Augsburg, Alemanha. Doutora Claire Maiza, Associate Professor do Grenoble INP Institute d’Ingénierie et de Management, Grenoble, França. Doutor Eduardo Manuel Medicis Tovar, Professor Coordenador do Departamento de Engenharia Informática do Instituto Superior de Engenharia do Instituto Politécnico do Porto (Orientador). Doutor João Paulo de Castro Canas Ferreira, Professor Associado do Departamento de Engenharia Eletrotécnica e de Computadores da Faculdade de Engenharia da Universidade do Porto. Doutor Mário Jorge Rodrigues de Sousa, Professor Auxiliar do Departamento de Engenharia Eletrotécnica e de Computadores da Faculdade de Engenharia da Universidade do Porto.

Conference or Workshop Papers/Talks
Open Questions for the Bus-Blocking Problem in the 3-Phase Task Model under Partitioned Scheduling CISTER-TR-210503 
Jatin Arora, Cláudio Maia, Syed Aftab RashidCAPITAL Workshop - sCalable And PrecIse Timing AnaLysis for multicore platforms (CAPITAL 2021). 4, Jun, 2021, Junior Presentations. Online.
Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned Scheduling CISTER-TR-210206 
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar29th International Conference on Real-Time Networks and Systems (RTNS 2021). 7 to 9, Apr, 2021, Technical Session. Online.
Open Issues in Analyzing the Schedulability for the 3-Phase Task Model using Partitioned Scheduling CISTER-TR-210603 
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Eduardo TovarThe symposium of “Electrical and Computer Engineering” of the 4th Doctoral Congress Engineering (DCE21) (DCE). 2021, Poster/Presentation Session. Online.
Technical Reports
Tightening the CRPD Bound for Multilevel non-Inclusive Caches CISTER-TR-211009 
Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar2021.