PReFECT
Predictable Multiprocessor Platforms for Embedded Safety Critical Systems
| POCI-01-0145-FEDER-029119 PTDC/CCI-COM/29119/2017 42 months (Jul 2018 to Jan 2022) | |
| Summary: | The PReFECT project will address the following challenges with respect to the introduction of multicore processors in safety-critical systems: - model and analyze the timing interference generated by the hardware resources shared between cores (e.g., caches, interconnect and I/O devices); - propose runtime mechanisms and scheduling solutions to mitigate the unpredictability of COTS multicore processors by controlling the interference between cores; - develop tools for the automatic system configuration before its deployment. The goal of this task is to optimize the usage of the platform while guaranteeing that all the timing requirements of the applications are respected. To attain these objectives we will build upon the large body of results already published by the research team on modelling and timing analysis of multicore processors, and on the expertise of the industrial partners (GMV and Critical Software) in the safety critical system development. The project results will be demonstrated in two industrial use-cases related to the avionics and automotive domains. |
| Funding: | Global: 237KEUR, CISTER: 237KEUR |
| Sponsors: |     |
| Partners: | |
| Contact Person at CISTER: | Eduardo Tovar |
14, Dec, 2021
Best Paper Award at ICESS 2021
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Journal Papers
Bus-Contention Aware WCRT Analysis for the 3-Phase Task Model Considering a Work-Conserving Bus Arbitration Scheme CISTER-TR-211004
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarJournal of Systems Architecture (JSA), Elsevier. 2022. (Best Paper of ICESS 2021) (ICESS 2021). 13 to 14, Jan, 2022, Volume Technical Session. Virtual, Australia.
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarJournal of Systems Architecture (JSA), Elsevier. 2022. (Best Paper of ICESS 2021) (ICESS 2021). 13 to 14, Jan, 2022, Volume Technical Session. Virtual, Australia.
PDFConference or Workshop Papers/Talks
Schedulability analysis for CAN bus messages of periodically-varying size CISTER-TR-220501
Ishfaq Hussain, Konstantinos Bletsas, Muhammad Ali Awan, Eduardo Tovar, Pedro Souto18th IEEE International Conference on Factory Communication Systems (WFCS 2022) (WFCS2022). 27 to 29, Apr, 2022, Deterministic and Predictable Industrial Communication. Virtual, Italy.
Ishfaq Hussain, Konstantinos Bletsas, Muhammad Ali Awan, Eduardo Tovar, Pedro Souto18th IEEE International Conference on Factory Communication Systems (WFCS 2022) (WFCS2022). 27 to 29, Apr, 2022, Deterministic and Predictable Industrial Communication. Virtual, Italy.
Cache-aware Schedulability Analysis of PREM Compliant Tasks CISTER-TR-220101
Syed Aftab Rashid, Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Eduardo TovarDesign, Automation and Test in Europe Conference (DATE 2022). 2022, Real-time, Dependable and Privacy-Enhanced Systems. ANTWERP, Belgium.
Syed Aftab Rashid, Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Eduardo TovarDesign, Automation and Test in Europe Conference (DATE 2022). 2022, Real-time, Dependable and Privacy-Enhanced Systems. ANTWERP, Belgium.