Syed Aftab Rashid joined the CISTER research unit in 2015 as a Ph.D. student. He is currently an integrated Ph.D. researcher and serves as CISTER lead at VORTEX-CoLab. He completed his Ph.D. from the University of Porto, Portugal, in 2021.

His dissertation was on the timing analysis of multicore platforms for hard real-time systems with a focus on contention due to sharing of cache memories and interconnects.

Before joining CISTER, he received his M.Sc. in Electrical Engineering from the National University of Computer and Emerging Sciences (NUCES)-FAST, Islamabad, Pakistan in 2014.

He has worked on several international projects related to embedded system design and implementation. He has also co-authored several publications in reputed conferences (e.g., RTSS, ECRTS, RTCSA, DATE) and journals (e.g., Applied Energy). Aftab has also been a part of different conference organization committees including ECRTS, RTNS, and CPSWeek.

His research interests include real-time embedded systems, timing and scheduling analysis, resource contention, and multicore architectures' predictability.