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4th Workshop on
High-performance and Real-time Embedded Systems
(HiRES 2016)
and
2nd
International Workshop on Dynamic Resource Allocation and Management
in Embedded, High Performance and Cloud Computing
January 19, 2016, Prague,
Czech Republic
in
conjunction with the
11th International Conference on
High-Performance and Embedded Architectures and Compilers (HiPEAC 2016)
https://www.hipeac.net/2016/prague/
HiRES
2016 and the second DREAMCloud Workshop will be
organised together. More information on DREAMCloud
available on http://www.dreamcloud-project.org/forum/workshop2016.
Goal of the HiRES Workshop
Increasingly, time
is a relevant concern which impacts in all application areas and challenges
ahead. Real-time requirements can be found in applications ranging from
large-scale data processing systems to deeply embedded devices. Examples
include safety-critical systems with high-performance requirements, such as
collision avoidance and autonomous driving in avionics and automotive
respectively, in which the correct timing behaviour is of paramount
importance; consumer systems, such as video processing in TV sets and
games; or real-time complex event processing applications, such as online
trading or real-time traffic management.
In all these applications,
systems are expected to cope with an increasing demand of functional and
non-functional requirements, with the corresponding increase in processing
capabilities, paving the way for high-performance architectures, of which
multi-core and many-core systems are becoming pervasive. The capabilities
and challenges of parallelization as a means to provide higher performance
is a cross-cutting concern.
This workshop intends to
bring together researchers and engineers in the confluence of
high-performance, embedded systems and real-time systems. The goal is to
allow for fruitful discussions on the challenges and research directions
that should be tackled by the community. Papers and presentations
illustrate current and future work in the theory and practice of the design
and engineering of high-performance real-time embedded systems for a
variety of application domains.
Program
14:00
Opening and Invited talk
Akash
Kumar (TU Dresden)
Design and
Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs
using Time-Series Analysis of Intermittent faults
Abstract: A large number of hardware faults are being
caused by an increasing number of manufacturing defects and physical
interactions during operation. This poses major challenges for the design
and testing of modern Multiprocessor System-on- Chips (MPSoCs).
Intermittent faults constitute a major part of hardware faults and their
fault rates can be used as an indicator of the wear-out in a Processing
Element (PE). We propose a run-time task re-mapping method that uses this
information to improve the useful lifetime of MPSoCs.
We also propose a scenario-aware system-level fault injection technique for
intermittent faults to evaluate system-level design techniques in MPSoCs. Our performance results conclusively show that
our strategy significantly scales on reliability metrics with respect to
number of PEs. Specifically, we show that our method can achieve an
increase in lifetime of up to 16% and tolerate up to 30% more faults than
state-of-the-art techniques.
14:35
Session 1: Dynamic Resource Management in HPC and Cloud Computing
Monitoring
in the Clouds: Comparison of ECO2Clouds and EXCESS Monitoring Approaches
Pavel
Skvortsov, Dennis Hoppe, Axel Tenschert
and Michael Gienger (HLRS, Universitaet
Stuttgart, DE)
A
Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud
Infrastructures
Roman
Ursu, Khalid Latif, David Novo, Manuel Selva, Abdoulaye Gamatie and Gilles Sassatelli
(LIRMM - University of Montpellier, FR)
Dmitry Khabi and Alexey Cheptsov
(HLRS, Universitaet Stuttgart, DE)
Bidding
policies for market-based HPC workflow scheduling
Andrew
Burkimsher and Leandro Soares Indrusiak
(University of York, UK)
Improving
virtual host efficiency through resource and interference aware scheduling
Evangelos Angelou, Konstantinos Kaffes,
Athanasia Asiki,
Georgios Goumas and Nectarios
Koziris (National Technical University of Athens,
GR)
15:35 Coffee break
16:00
Session 2: Predictable Resource Management in Multiprocessor Embedded
Systems
Benchmarking,
System Design and Case-studies for Multi-core based Embedded Automotive
Systems
Piotr
Dziurzanski, Amit Singh and Leandro Soares
Indrusiak (University of York, UK)
Holistic
Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems
Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan and Thomas Hollstein (Tallinn University of Technology, EE)
Design
and validation of a multi-core embedded platform under high performance
requirements
Vittoriano Muttillo (University of L'Aquila, IT)
Guaranteeing
predictable parallel behavior in the P-SOCRATES architecture
Luis
Miguel Pinho (CISTER - IPP, Porto, PT)
17:00
Invited talk
Gerard
Rauwerda (RECORE)
Many-core
processor architectures; fault-tolerance and programmability
Abstract: Massive many-core SoCs
– like many other designs – are often designed with the focus on the
hardware. The programming models for these complex many-cores often come as
an afterthought and programmers have to make do with what is designed into
the hardware. This gives many-core programming a reputation of being a
programmer’s nightmare. In this talk, Gerard will present Recore's FlexaWare approach. FlexaWare® is a flexible and scalable embedded
processing platform that unites easy programming and heterogeneous
many-core system complexity. The embedded platform combines hardware, a
runtime and a software development environment. Also, he will explain Recore's contribution to several European FP7/H2020
research projects with respect to many-core programming issues as well as
fault-tolerance.
Topics of interest
Topics of interest to this
edition of the workshop include but are not limited to:
-
Runtimes
and operating systems combining high-performance and predictability
requirements;
-
Programming
models and compiler support for providing real-time capabilities to multi-
and many-core architectures;
-
Models
and tools for code generation, system verification and validation;
-
Worst-case
execution time analysis, parallel/dag-based task models, schedulability
analysis of multi- and many-core systems;
-
Heterogeneous
multi-core embedded real-time architectures, many-core accelerators;
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Time-predictable
multi- and many-core processor architectures;
-
Time-aware
energy-efficiency.
Organizers
Luís Miguel Pinho, CISTER,
Portugal
Eduardo Quiñones, BSC,
Spain
Sascha Uhrig, Airbus Group
Innovations, Germany
Program committee
Albert Cohen, INRIA, France
Alejandro Alonso, Universidad Politécnica de
Madrid, Spain
Andrea Marongiu, ETHZ,
Switzerland
Eduardo Quiñones, BSC,
Spain
Johan Eker, Ericsson,
Sweden
Luís Miguel Pinho, CISTER, Portugal
Marko Bertogna, University of Modena, Italy
Martin Schoeberl, DTU,
Denmark
Neil Audsley, University of
York, UK
Philippe Bonnot, Thales,
France
Sascha Uhrig, Airbus Group
Innovations, Germany
Theo Ungerer, University of
Augsburg, Germany
Zlatko Petrov, Honeywell,
Czech Republic
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