Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis
Ref: CISTER-TR-130105 Publication Date: 18 to 22, Mar, 2013
Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis
Ref: CISTER-TR-130105 Publication Date: 18 to 22, Mar, 2013Abstract:
The transition towards multi-processor systems with shared resources is challenging for real-time systems, since resource interference between concurrent applications must be bounded using timing analysis. There are two common approaches to this problem: 1) Detailed analysis that models the particular resource and arbiter cycle-accurately to achieve tight bounds. 2) Using temporal abstractions, such as latency-rate (LR) servers, to enable uni fied analysis for di fferent resources and arbiters using well-known timing analysis frameworks. However, the use of abstraction typically implies reducing the tightness of analysis that may result in over-dimensioned systems, although
this pessimism has not been properly investigated.
This paper compares the two approaches in terms
of worst-case execution time (WCET) of applications
sharing an SDRAM memory under Credit-Controlled
Static-Priority (CCSP) arbitration. The three main
contributions are: 1) A detailed interference analysis of
the SDRAM memory and CCSP arbiter. 2) Based on
the detailed analysis, two optimizations are proposed
to the LR analysis that increase the tightness of its
interference bounds. 3) An experimental comparison of
the two approaches that quantifi es their impact on the
WCET of applications from the CHStone benchmark.
Hardik Shah
Benny ÅkessonDocument:
View
DownloadDesign, Automation & Test in Europe Conference & Exhibition (DATE 2013), IEEE, pp 308-313.
Grenoble, France.
DOI:10.7873/DATE.2013.075.
Record Date: 15, Jan, 2013